(1) Field of the Invention PA1 (2) Description of the Prior Art
This invention relates to the fabrication of integrated circuit devices and more particularly to a method of making self-aligned and closely spaced polysilicon bit lines and word lines for read only memory (ROM) and the like.
Lithography resolution is limited by optical design. The technology of read only memory is therefore limited, because of the inability to form very closely spaced polycrystalline silicon (polysilicon) conductor lines over the surface of a read only memory.
Researches in the integrated circuit field generally have used the sidewall technology to form smaller spaces than normally available through lithography for various purposes. Examples of this type of application is shown in U.S. Pat. No. 4,502,914 to H.J. Trumpp et al; U.S. Pat. No. 4,839,305 to J.K. Brighton and U.S. Pat. No. 4,868,136 to A. Ravaglia.
However, in the read only memory field the researchers have used two layer polysilicon structures to make more densely packed memories such as described in Y. Naruke U.S. Pat. No. 5,002,896. While these have been successful, it is clear that if a single layer, closely spaced technology were available there are advantages over the two layer structures. One advantage for the single layer structure is in the planarity of the surface over a two layered structure. Other advantages are cost effectiveness and process simplicity.